An integrated circuit, currently known as a chip, is essentially a semiconductor substrate including doped regions for defining electronic components and having an interconnect structure for these components. The interconnect structure rests on the substrate via a dielectric silicon dioxide (SiO.sub.2) layer formed by growth of the material of the substrate. Generally, the dielectric layer is thin (several tens of nanometers thick) above the doped regions, and thick (several nanometers thick) between these regions. The interconnect structure presently comprises a plurality of conductive layers separated by insulating layers and connected to one another at certain points by vias passing through the insulating layers. Each conductive layer comprises numerous conductors parallel to one another in a direction orthogonal to the conductors of a neighboring conductive layer. Conductors of the lower layer are connected with the corresponding regions of the substrate via openings made in the thin dielectric layer covering these regions.
At present in the manufacture or design of very large scale integrated circuits, or VLSI chips, attempts are being made to make wide use of the laser to modify the circuits on these chips. In particular, modification of the circuits of a chip is done to correct certain connection defects. Connections made by laser are then programmed for reconfiguring a circuit because of a defect, or to connect a substitute circuit to a defective circuit in accordance with the technique known as redundancy of the functional blocks of an integrated circuit. On the other hand, modification of the integrated circuits in a chip naturally takes place when the chip is, or includes, a programmable read only memory (PROM). The conduction state of the cells of the memory is determined by one or more connections between predetermined conductor elements of each cell. The use of the laser is one solution intended for programming a PROM. In conclusion, laser programming of the connections in the integrated circuits of a chip has numerous applications and numerous advantages.
Several methods are now known for making an electrical connection of two superimposed conductors of an integrated circuit, or between a conductor and a region of the substrate, at a point through the thin dielectric layer by laser beam.
One known method of programmable bonding by laser of two superimposed conductors is described in particular in the article by N. S. Platakis in the Journal of Applied Physics, Vol. 47, No. 5, May 1976, pp. 2120-2128. At the desired bonding point, a laser beam is applied, the energy, diameter, number and duration of the pulses of which are determined so as to progressively open the upper conductor, then the dielectric layer and, partially, the lower conductor and to form a contact between the two conductors by ejecting melted material of the lower conductor up to the level of the upper conductor. Then the two conductors are connected to one another by the solidified ejections on the walls of a crater, which thus has the approximate shape of a metallized hole. This method has numerous disadvantages.
First, it will be understood that the uncontrollable ejections of melted material of the lower conductor placed beneath a laser beam, under identical conditions, yield different configurations of the band of the conductors in each crater. As a result, the bonds formed by this method, under identical conditions, have different electrical connection qualities. Experience has confirmed the defects in terms of replicability and reliability of this method.
As a second disadvantage, the formation of a crater requires the use of a powerful laser beam and damages the structure of the two conductor elements and the insulating layer separating them. On the one hand, the thermal shock can create electrical defects in the active elements (junctions, transistors, and so forth) which surround the crater. On the other hand, the thermal shock creates a dislocation of the structure of the conductor elements, which is particularly undesirable when the lower conductor element is a doped region of a silicon substrate. Even if the lower element is a conductor of the interconnect structure, this element must have a minimum thickness so as not to damage the insulating layer that separates it from the substrate. Consequently the connection by laser, in the form of a crater, is limited in practice to the connection of two conductor elements of the interconnect structure formed above a silicon substrate. It follows that for a desired connection between an upper conductor and a doped region of the substrate, this region must be connected to an intermediate conductor, with which the upper conductor will be connected by a crater sufficiently distant from the doped region of the substrate.
Another disadvantage of this connection method is that it cannot be done after the manufacture of the integrated circuit. The manufacture of an integrated circuit ends with the covering of the entire interconnect structure with a thick passivation layer adapted for protecting the integrated circuit electrically, mechanically and chemically. It will be understood then that laser connection cannot be done correctly except prior to the deposition of the passivation layer, that is, during the process of manufacture of the integrated circuit. This disadvantage translates into a lack of flexibility in programming the bonds in the integrated circuit and an increase in cost.
Finally, connection at one point by laser in the form of a crater is easily observable by optical microscope, and an observer can learn the entire configuration of the connections made on an integrated circuit from it. This kind of connection thus cannot be used when the connections are part of confidential information or that are to remain inviolable, as is the case for example for integrated circuit memories in credit cards (known as smart cards).
Another known method for programmable bonding by laser of two superimposed conductors is described in particular in the article by J. I. Raffel et al, entitled "Laser Programmed Vias for Restructurable VLSI" in the publication "Technical Digest of the International Electron Devices Meeting", 1980, pp. 132-135. This method comprises using amorphous silicon in the dielectric layer at the level of the bonding point. The use of amorphous silicon in predetermined regions of the dielectric layer has the disadvantage of complicating the method of manufacturing the integrated circuit and of prohibiting programming any bonds by laser outside these regions.
The invention proposes a method of connection by laser of a conductor element to a doped region of the substrate of an integrated circuit, which has the advantage over the prior methods of being simple, reliable and effective, with a less powerful laser, which is usable during and after the manufacture of the integrated circuit and leaves practically no trace that is detectable by microscope of the connection that has been made.